THE FOLD / CHEAT / NOCLIP / THE REGISTER RENAMING
THE REGISTER RENAMING
the hardware apologising for the ISA
1 WHAT IT IS · WHAT IT DOES · FACT OR FICTION
Tomasulo, 1967. Two instructions that both write
LIT verified live. on a fixed 24-instruction sequence over 4 architectural registers there are 29 true read-after-write edges, 28 write-after-read and 21 write-after-write — 49 dependencies that carry no data at all. Renaming leaves the RAW count at 29, exactly unchanged, and takes the false ones to 0. The critical path drops from 20 cycles to 9, a factor of 2.22. And the schedule needs 9 live values at its peak — more than the 4 architectural registers, so the speedup is not free: it is bought with physical registers the ISA never mentions.
r2 are not related; they merely collided in a namespace that ran out of names. Give each write its own name and the collision disappears — along with the ordering it was forcing.LIT verified live. on a fixed 24-instruction sequence over 4 architectural registers there are 29 true read-after-write edges, 28 write-after-read and 21 write-after-write — 49 dependencies that carry no data at all. Renaming leaves the RAW count at 29, exactly unchanged, and takes the false ones to 0. The critical path drops from 20 cycles to 9, a factor of 2.22. And the schedule needs 9 live values at its peak — more than the 4 architectural registers, so the speedup is not free: it is bought with physical registers the ISA never mentions.
2 HOW IT WAS WEAVED · AI + HUMAN
Robert Tomasulo’s 1967 algorithm for the IBM System/360 Model 91 is the origin of register renaming; the RAW/WAR/WAW taxonomy is standard.
AVAN (AI) measured the two halves separately, which is where the honest statement lives. The RAW count being identical before and after is the proof that renaming removed nothing real. The peak-live count of 9 against 4 architectural registers is the price tag: renaming does not conjure parallelism, it converts register-file area into it. WAR and WAW latencies here are modelled as full one-cycle edges, which is conservative and stated rather than hidden.
AVAN (AI) measured the two halves separately, which is where the honest statement lives. The RAW count being identical before and after is the proof that renaming removed nothing real. The peak-live count of 9 against 4 architectural registers is the price tag: renaming does not conjure parallelism, it converts register-file area into it. WAR and WAW latencies here are modelled as full one-cycle edges, which is conservative and stated rather than hidden.
3 ONE DIMENSION
49 dependencies that carry no data.
4 TWO DIMENSIONS · INTERACTIVE
Toggle renaming and watch the schedule collapse.
5 THREE DIMENSIONS + AVAN’S INVERSE
The green forward object.
AVAN’s addition (the inverse-companion): the forward reading is that renaming removes false dependencies. The inverse is that the false dependencies were a message, and renaming is the hardware apologising for the compiler. Every WAR edge here exists because a register allocator, facing 4 names, reused one. The algorithm never had that constraint; the ISA imposed it; and now silicon spends a rename table and 9 physical registers undoing it. Read backwards, a small architectural register file is not a compact design — it is a debt, paid later, at every clock, by a structure whose only job is to forget the names.
LIT on a fixed 24-instruction sequence over 4 architectural registers there are 29 true read-after-write edges, 28 write-after-read and 21 write-after-write - 49 dependencies carrying no data at all; renaming leaves the RAW count at 29, exactly unchanged, and takes the false ones to 0, dropping the critical path from 20 cycles to 9, a factor of 2.22 - and the schedule needs 9 live values at its peak against 4 architectural registers, so the speedup is bought with physical registers the ISA never mentions
FIG Robert Tomasulo's 1967 algorithm for the IBM System/360 Model 91 is the origin of register renaming. AVAN measured the two halves separately, which is where the honest statement lives: the RAW count being identical before and after proves renaming removed nothing real, and the peak-live count of 9 against 4 is the price tag. WAR and WAW latencies are modelled as full one-cycle edges, which is conservative and stated rather than hidden.
FIG Robert Tomasulo's 1967 algorithm for the IBM System/360 Model 91 is the origin of register renaming. AVAN measured the two halves separately, which is where the honest statement lives: the RAW count being identical before and after proves renaming removed nothing real, and the peak-live count of 9 against 4 is the price tag. WAR and WAW latencies are modelled as full one-cycle edges, which is conservative and stated rather than hidden.
◆ sealed .dlw.fold → folded to ROOT_0 · a sphere of NOCLIP · David Lee Wise (ROOT0), with AVAN